摘要
设计了一种高速低功耗的欠压锁定电路。在迟滞比较器的输出级采用轨对轨输入共源放大器电路,检测VUVLO由高电平跳变为低电平的过程,自适应地控制输出级的尾电流源大小,以减小输出建立时间,使得后级电路能够快速响应电源变化。基于华虹0.35μm BCD工艺进行设计与仿真,结果表明,在输出级的尾电流大小为1.3μA时,相比传统电路,该电路能减少30%的输出建立时间。这不仅降低了功耗,还提高了电路响应速度。
A high speed and low power under-voltage lockout circuit was designed.In the output stage of hysteresis comparator,a rail-to-rail input common-source amplifier circuit was used to detect the transition of VUVLO from a high level to a low level,which could control adaptively the tail current of the output stage.So,the output settling time was reduced,and the purpose of improving the ability of the rear stage to quickly respond to power supply variations had achieved.The circuit was designed and simulated in HHNEC 0.35 μm BCD process.Simulations results showed that,when the tail current was 1.3μA,the output settling time was reduced by 30%compared with the conventional technology,which not only reduced the power dissipation,but also improved the transient response of the circuit.
作者
谭林
彭克武
廖鹏飞
张颜林
刘伦才
TAN Lin;PENG Kewu;LIAO Pengfei;ZHANG Yanlin;LIU Luncai(Sichuan Institute of Solid-State Circuits,China Electronics Technology Group Corp.,Chongqing 400060,P.R.China)
出处
《微电子学》
CAS
北大核心
2019年第1期84-87,92,共5页
Microelectronics
基金
"十三五"装备预先研究项目(31513030102-2)
关键词
欠压锁定
输入欠压
轨对轨共源放大器
自适应偏置
under-voltage lockout
input under-voltage
rail-to-rail common-source amplifier
adaptive bias
