摘要
根据Moore型有限状态机的原理,对内存控制器的设计提出了普通型、时钟同步输出信号型和直接把状态作为输出信号型(Outputs=states)三种VHDL设计方法,并从消除"毛刺",提高资源利用率和速度等方面对三种方法进行了比较.通过开发工具Max+plusⅡ的编译和功能仿真,验证了方法的合理性和通用性.
According to the principle of moore type FSM,three VHDL design methods are disscussed to design mainmemory controller in this paper.The common and 'sync outputs with clock' and 'out puts=states'type FSM are given specially. At the same time this paper compares the ways to remove burr and increase resources utilization ratio and control velocity ect. A practical example tests that the way is retional and general by compiler and simulation of Max+plusⅡ.
出处
《兰州铁道学院学报》
2003年第1期90-93,共4页
Journal of Lanzhou Railway University
