摘要
JESD204B协议的广泛运用以及其带来的好处,为雷达接收机提高集成度实现高速采集提供了可能。介绍了采用基于JESD204B协议的AD9680 ADC与可实现ESD204B协议数据帧解码的FPGA的高速雷达数字接收机的设计,简述了该接收机的系统架构,详细地阐述了数据帧解码的软件设计以及结合FPGA逻辑分析软件Chipscope和Matlab程序对系统的指标进行测试。
The JESD204 B protocol has many benefits and has been widely used,So It is possible to improve the integration of radar receiver to realize high speed acquisition. The design of radar receiver with ADC and FPGA is introduced in this paper.The ADC based on the JESD204 B protocol can be used to realized radar echo data acquisition. The system architecture is briefly described and The design of data frame and the method of decoding are analyzed in detail, the technical specification is tested using the tools of Chipscope and Matlab.
出处
《信息通信》
2016年第6期42-44,共3页
Information & Communications
