摘要
针对传统引信感应装定系统中未能进行差错控制编码而在接收端出现码元传输错误不能进行纠错的问题,基于FPGA设计了一套应用于引信装定系统的高速RS(15,9)编码器。RS码是线性分组码中一种典型的纠错码,既能纠正随机错误又能纠正突发错误,在现代通信领域中越来越受到重视。介绍了RS编码器的设计方法,优化了其中乘法器的设计,并利用Verilog语言在QuartusII 12.1上实现了功能仿真,仿真结果与理论分析一致。利用Altium Designer设计了FPGA最小系统电路,实现了程序与硬件的联调,完成了RS编码器的设计。
Based on FPGA, a high speed RS(15,9) encoder used in fuze setting system is designed to solve the problem that error control coding can not be carried out in the traditional fuze induction setting system and error correction can not be made at the receiver. RS code is a typical error correcting code in linear block code, which can correct both random error and burst error. It has been paid more and more attention in the field of modern communication. This paper introduces the design method of RS encoder, optimizes the design of the multiplier, and uses the Verilog language to realize the function simulation on QuartusII 12.1, and the simulation result is consistent with the theoretical analysis. The minimum system circuit of FPGA is designed by using Altium Designer, and the program and hardware are debugged to complete the design of RS encoder.
作者
张欣伟
王鹏
Zhang Xinwei;Wang Peng(Electronic Information Engineering College,Xi′an Technological University,Xi′an 710021,China)
出处
《国外电子测量技术》
2019年第1期112-115,共4页
Foreign Electronic Measurement Technology
