摘要
为了提高低密度奇偶校验码(LDPC)译码器的译码速度,提出了一种基于图形处理单元(GPU)加速的并行LDPC译码方案。该方案基于对数似然比(LLR-BP)译码算法进行设计,针对算法的可并行部分采用并行度更高的边并行译码方案,以降低译码延迟并提高了GPU的线程利用率。此外,通过优化线程分配策略,将变量节点更新的信息存储在访问成本更低的共享内存中,减少了消息传递过程中对全局内存的依赖。实验结果表明,所提方案的译码速度分别是传统的节点并行译码和边并行译码方案的2.8倍和1.2倍,满足高速通信系统的需求。
To improve the decoding speed of low density parity check(LDPC)decoders,a parallel LDPC decoding scheme accelerated by graphics processing units(GPU)is proposed.This scheme is designed based on the log-likelihood ratio belief propagation(LLR-BP)decoding algorithm and adopts a higher parallelism edge-parallel decoding approach for the parallelizable parts of algorithm to reduce decoding latency and enhance the thread utilization rate of GPUs.In addition,by optimizing the thread allocation strategy,the updated information of variable nodes is stored in shared memory with lower access costs,reducing the dependence on global memory during message transmission.The experimental results show that the decoding speed of the proposed scheme is 2.8 times and 1.2 times that of the traditional node-parallel and edge-parallel decoding schemes,which can meet the needs of high-speed communication systems.
作者
黄柯文
刘世刚
汪洋
HUANG Kewen;LIU Shigang;WANG Yang(Zhongyuan University of Technology,Zhengzhou 451191,China)
出处
《电子质量》
2024年第10期43-48,共6页
Electronics Quality
