摘要
处理器片上寄存器的分布形态与数量规模对处理器的整体计算性能有直接影响,这种影响表面上看是波及处理器片上缓存结构的改进和优化,本质上是时间要素与空间要素交织在一起的综合反映.因此,从时间和空间上确保处理器内核对片上缓存的局部化访问必将进一步提高处理器的整体计算性能.为了认识处理器片上缓存中存在的时间与空间及时局部性,以由传统缓存耦合而成的渗透缓存为工具来分析处理器内核访问片上缓存的时间与空间局部性,仿真实验表明渗透缓存因具备容纳时间与空间局部性的结构提高了处理器访问片上缓存的命中率,客观上缩短访存延迟,从而为提高处理器性能创造了有利条件.
It is believed that the arrangements and amounts of the registers in processor chip have much heavy impact on the operation speed of the processor,which has induced the improvement of the structure of the on-chip cache,whose central task is to realize the fast access to the data in registers in the term of time and space.This kind of fast access to the register can be investigated vise the access process in which the data and structures in on-chip cache are accessed.By introducing the a new on-chip cache percolation cache,we prove that the existent of the time and spatial just-in-time locality which the percolation cache equips has contributed much to shorten the memory access delay by raising the hit rates when processor core accesses the percolation cache.
作者
胡九川
程建聪
万良易
吴楠士
叶笑春
严龙
HU Jiu-chuan;CHENG Jian-cong;WAN Liang-yi;WU Nan-shi;YE Xiao-chun;YAN Long(School of Computer and Information Technology,Beijing Jiaotong University,Beijing 100044,China;Center for Information of Education Management,Ministry of Education,Beijing 100816,China;The 32nd Research Institute of China Electronics Technology Group Corporation,Shanghai 201800,China;State Key Laboratory of Computer Architecture,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190,China)
出处
《电子学报》
EI
CAS
CSCD
北大核心
2024年第10期3589-3599,共11页
Acta Electronica Sinica
基金
国家自然科学基金(No.62202451)。
