摘要
高速接口芯片是高性能互连网络通信中的一款重要IP,针对56 Gb/s四脉冲幅度调制信号在高性能互连网络背板通信中,由于传输距离长信道衰减严重导致误码率高的问题,提出一种面向56 Gb/s高速Serdes接收机DSP设计。该DSP采用64路并行结构,通过16抽头前向反馈均衡器,以及1抽头预判决反馈均衡器对接收端数字化后的信号进行处理;采用基于K-均值聚类算法生成动态变化的判决电平并结合最小均方误差算法,能够处理15~35 dB不同信道衰减下的均衡问题。为了验证算法的性能,还搭建了一个基于模拟前端芯片和现场可编程门阵列的实验验证平台。实验结果表明,在信道衰减为15~35 dB@14 GHz,速率为56 Gb/s的条件下,误码率均小于5e-10。
The high-speed serial interface chip is an important IP in high-performance interconnect network communication.This paper proposes a DSP design for 56 Gb/s high-speed Serdes receivers,in response to the problem of high bit error rate caused by severe channel attenuation over long transmission distances in high-performance interconnect network backplane communication using 56 Gb/s four pulse amplitude modulation(PAM4)signals.The DSP adopts a 64-channel parallel structure and processes the digitized signal from the receiver through a 16-Tap feed forward equalizer(FFE)and a decision feedback equalizer(DFE).By using the K-means clustering algorithm to generate dynamically changing DFE decision levels and combining it with the least mean square(LMS)algorithm,it can handle the equalization problem under different channel attenuation of 15~35 dB.To verify the performance of the algorithm,an experimental verification platform based on analog frontend chips and field programmable gate arrays(FPGA)was constructed.The experimental results indicate that the channel attenuation is 15~35 dB@14 GHz at a speed of 56 Gb/s,the error rate is less than 5e-10.
作者
胡小月
王强
吕方旭
许超龙
张锦
HU Xiao-yue;WANG Qiang;L Fang-xu;XU Chao-long;ZHANG Jin(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;School of Computer and Communication Engineering,Changsha University of Science&Technology,Changsha 410004,China)
出处
《计算机工程与科学》
CSCD
北大核心
2024年第7期1202-1209,共8页
Computer Engineering & Science
基金
国家重点研发计划(2021YFB2206600)。
关键词
K-均值算法
前向反馈均衡
预判决反馈均衡
自适应均衡
K-means algorithm
feed forward equalization
decision feedback equalization
adaptive equalization
