摘要
SM4加解密算法作为我国第一个商用密码算法,凭借其算法结构简单易实现、加解密速度快和安全性高等优点,被广泛应用在数据加密存储和信息加密通信等领域中。以可变流水级SM4加解密算法硬件设计以及FPGA实现为研究课题,重点研究了不同流水线级数设计的性能差异,设计了一种可控制流水线级数的SM4加解密电路,并将其封装为带有AXI接口和APB接口的IP核。基于XILINX ZYNQ器件,在XILINX ZYNQ-7020开发板上搭建小型SoC,将设计的SM4 IP核挂载到AXI总线上,模拟实际工作情景并进行性能测试。通过软件加解密数据与仿真测试得到的数据来验证设计功能的正确性;测试不同流水线级数的性能,以此选出最适合的流水线级数。
As the first commercial cryptographic algorithm in China,SM4 algorithm is widely used in data encryption storage and information encryption communication and other fields due to its advantages of simple and easy implementation of algorithm structure,fast encryption and decryption speed and high security.With the variable pipeline stage SM4 encryption and decryption algorithm hardware design and FPGA implementation as the research topic,this study focuses on the performance differences in designs with different pipeline stages.A controllable pipeline stage SM4 encryption and decryption circuit is designed and encapsulated into an IP core with AXI and APB interfaces.Based on XILINX ZYNQ devices,a small SoC is constructed on the XILINX ZYNQ-7020 development board,and the designed SM4 IP core is mounted onto the AXI bus for simulating real-world scenarios and conducting performance tests.The correctness of the design functionality is verified by comparing software encryption and decryption data with simulated data.Testing the performance of different pipeline stages helps identify the most suitable pipeline stage number.
作者
朱麒瑾
陈小文
鲁建壮
ZHU Qi-jin;CHEN Xiao-wen;LU Jian-zhuang(College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;Key Laboratory of Advanced Microprocessor Chips and Systems,Changsha 410073;School of Integrated Circuit Science and Engineering,University of Electronic Science and Technology of China,Chengdu 610054,China)
出处
《计算机工程与科学》
CSCD
北大核心
2024年第4期606-614,共9页
Computer Engineering & Science
