摘要
高速中等精度的模数转换器是通信系统中重要的组成部分。本文提出了一种基于分段冗余电容阵列的高速逐次逼近型模数转换器(SAR ADC)设计方案。该设计方案通过引入分段冗余电容阵列,在降低了面积和功耗的同时,克服了高速采样下,DAC不完全建立对ADC性能的影响。所设计的两级动态比较器,通过噪声分析可知,在满足高速性能的前提下,提高了ADC的精度。基于SMIC55nm CMOS工艺,本文实现了一种12-bit 100-MS/s的SAR ADC。在1.2V电源电压和100MS/s的采样频率,差分输入接近满摆幅下,前仿真结果为SNDR为73.27dB,ENOB可达11.87bit。
Analog-to-digital converter is a significant block in communication system which requires high sampling rate and high resolution.This paper proposed a high-speed successive approximation analog-to-digital converter(SAR ADC)based on segmented redundant capacitor array.By introducing a segmented redundant capacitor array,the design scheme can reduce the area and power consumption,and tackles the insufficient DAC settling on ADC performance under high-speed sampling.Through noise analysis,a two-stage dynamic comparator is designed,and the accuracy of ADC is improved under the premise of high-speed performance.The proposed SAR ADC is designed in SMIC55nm CMOS technology with the supply voltage of 1.2V and sampling frequency of 100MS/s,the pre-simulation result shows that SNDR is 73.27dB and ENOB is up to 11.87bit.
作者
林思远
LIN Si-yuan(College of Physics and Information Engineering,Fuzhou University)
出处
《中国集成电路》
2024年第3期72-77,共6页
China lntegrated Circuit
