摘要
针对帧间预测重构时,因编码树单元(CTU)尺寸增大和划分层次增加,完成全部变换块变换所需要的时钟周期显著增多的问题,提出一种既可以实现单一变换块的变换与反变换,又可以对尺寸为32 px×32 px、基于高效视频编码标准(HEVC)四叉树划分的混合块进行变换与反变换的硬件架构.采用多层次蝶形架构与混合矩阵乘法器对混合输入数据进行逐级分解并运算.实验结果显示,其数据流动与单一变换块一致.在Altera的Stratix III器件下综合工作频率为189.47 MHz;在Synopsys的SAED 90-nm器件库下用逻辑综合工具(DC)综合工作频率为140 MHz,逻辑门数为1.30×10^(5);混合块变换每个时钟始终可以处理32点数据.
Aiming at the problem that the clock cycle required to complete the transformation of all transform blocks increases significantly with the increase of coding tree unit(CTU)size and partition level during inter prediction reconstruction,proposes a hardware architecture that can not only realize the transformation and inverse transformation operation of a single transformation block,but also transform and inverse transform the mixed block with the size of 32 px×32 px divided by high efficiency video coding(HEVC)quadtree.The multi-level butterfly architecture and hybrid matrix multiplier are used to decompose and calculate the mixed input data step by step,and its data flow is consistent with that of a single transformation block.Under Altera’s Stratix III device series,the comprehensive working frequenc y is 189.47 MHz.Under Synopsys’s SAED 90-nm device library,the design compiler(DC)comprehensive workin g frequency is 140 MHz,the number of logic gates is 1.30×10^(5),each clock can always process 32 points of data under the mixed block transformation.
作者
兰尔铭
施隆照
宋佳柔
杨小玲
LAN Erming;SHI Longzhao;SONG Jiarou;YANG Xiaoling(College of Physics and Information Engineering,Fuzhou University,Fuzhou,Fujian 350108,China)
出处
《福州大学学报（自然科学版）》
CAS
北大核心
2023年第4期505-511,共7页
Journal of Fuzhou University(Natural Science Edition)
基金
福建省自然科学基金资助项目(2022J01083)
福建省教育厅"2020年福建省高等学校科技创新团队(产业化专项)(500190)。
关键词
高效视频编码
离散余弦变换
硬件架构
现场可编程门阵列
逻辑综合
high efficiency video coding
discrete cosine transform
hardware architecture
field programmable gate array
design compile
