摘要
在低功耗设计中,多电源多电压技术通常使用电源状态表格(Power State Table,PST)定义各个电压域的供电状态组合.当PST数量较多时,EDA(Electronic Design Automation)对PST的合并速度很慢.针对这个问题,提出一种基于分治思想的数字集成电路低功耗供电网络建模方法.其利用分治算法将供电网络分割成个子模块,并使用二分查找和哈希算法对建模过程进行优化,使建模速度相比线性查找平均提高了约三分之一.然后使用双重映射算法和并行计算将模型中所有PST快速合并.最后设计UPF测试集以验证模型的正确性和测试模型的分析速度.在500个UPF(Unified Power Format)文件测试中,分析结果正确率为100%.在10个性能测试集中发现相比国际主流的LP工具,速度提高约115倍.
In low-power design,the multi-power multi-voltage technology usually uses the Power State Table(PST)to define the power state combination of each voltage domain.When the number of PSTs is large,EDA(Electronic Design Automation)is slow in merging PSTs.Aiming at this problem,this paper proposes a modeling method of low-power power supply network of digital integrated circuits based on the idea of divide and conquer.It uses the divide and conquer algorithm to divide the power supply network into sub-modules,and uses binary search and hash algorithm to accelerate the modeling process.Optimized to increase modeling speed by an average of about one-third over linear search.All PSTs in the model are then quickly merged using a dual mapping algorithm and parallel computation.Finally,the UPF test set is designed to verify the correctness of the model and test the analysis speed of the model.In the test of 500 UPF(Unified Power Format)files,the correct rate of analysis results is 100%.In 10 performance test sets,it is found that the speed is about 115 times faster than that of the international mainstream LP tools.
作者
蒋润发
李海华
刘洋
刘军
JIANG Runfa;LI Haihua;LIU Yang;LIU Jun(School of Electronic Information and Electrical Engineering,Shanghai Jiao Tong University,Shanghai 200240,China;X-EPIC,Nanjing 210000,China)
出处
《微电子学与计算机》
2023年第7期111-117,共7页
Microelectronics & Computer
基金
国家自然科学基金(61574093)。
关键词
低功耗
电子设计自动化
建模
多电源电压
数字集成电路
电源状态表格
Low power
Electronic design automation
Modeling
Supply network
Digital integrated circuits
Power state table
