摘要
提出一种适用于片上系统的时钟与复位管理电路,并搭建验证平台予以验证。该设计集成复位信号生成电路、复位同步释放电路、基准电压源、压控振荡器、锁相环、时钟门控电路等。数字电路设计基于180 nm标准单元库搭建,基于System Verilog语言搭建了一个功能完备的自动化测试平台,代码覆盖率与功能覆盖率达到100%。相比传统设计,该电路所有单元均在内部,集成度高、可靠性强。
In the paper,a clock and reset management circuit for system-on-chip is designed,and builds a verification platform for verification.The design integrates reset signal generation circuitry,reset synchronous release circuit,voltage reference,voltage controlled oscillator,phase-locked loop,clock gate circuit,etc.The digital circuit design is based on the 180 nm standard unit library,and a fully functional automated test platform is built based on the System Verilog language,with code coverage and functional coverage of 100%.Compared with the traditional design,all units of the circuit are internal,with high integration and high reliability.
作者
李超
赵启林
戴兆麟
刘璐
Li Chao;Zhao Qilin;Dai Zhaolin;Liu Lu(Electronics and Information Engineering,Shanghai University of Electric Power,Shanghai 201306,China;Moore Integrated Circuit Industry Development Co.,Ltd.)
出处
《单片机与嵌入式系统应用》
2023年第6期8-11,16,共5页
Microcontrollers & Embedded Systems
关键词
SOC
时钟管理
复位管理
覆盖率
功耗控制
SoC
clock management
reset management
coverage
power consumption control
