摘要
提出了一种高可靠性的嵌入式系统电源设计方案,出现外部供电欠压故障后触发嵌入式系统各电源轨下电,并在外部供电电压恢复正常后先产生时长可调的延时信号,保证各级电源轨完全下电后再按照设计的时序重新上电,确保每次上电时序正常。本文结合主流嵌入式处理器的供电时序要求,对所提设计方案从理论上进行分析,并计算所需参数,最后通过仿真以及实验测试验证所提设计方案的可行性。
In the paper,a high reliability embedded system power supply scheme is proposed.After the external power supply undervoltage fault occurs,each power rail in the board is triggered to be powered off,and after the external power supply voltage returns to normal,the time-delay signal with adjustable length is generated first,so as to ensure that the power rails at all levels are completely powered off and then powered on again according to the designed timing,so as to ensure that the timing of each power on is normal.Combined with the power supply timing requirements of mainstream embedded processors,the proposed design scheme is analyzed theoretically,and the required parameters are calculated.Finally,the feasibility of the proposed design scheme is verified by simulation and experimental tests.
作者
陈继洪
Chen Jihong(Guodian Nanjing Automation Company Limited,Nanjing 211153,China)
出处
《单片机与嵌入式系统应用》
2023年第4期28-32,共5页
Microcontrollers & Embedded Systems
关键词
嵌入式系统
上电时序
电源
embedded system
power supply
power supply
