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电容隔离式栅极驱动电路设计

Design of capacitive-isolation gate drive circuit
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摘要 针对功率半导体器件不断提升的开关频率和工作电压等级使得传统的栅极驱动电路面临着传输延时长、共模瞬态抑制能力(CMTI)不高等一系列缺点,设计了一种电容隔离式的栅极驱动电路,该驱动电路分为低压侧发射端和高压侧接收端2个部分。提出了一种预放大器结构可增强栅极驱动电路的抗噪声能力;也提出了一种改进型包络解调结构可有效降低信号解调的脉冲宽度失真。后仿真结果表明:此栅极驱动电路的CMTI能力高达100 kV/μs,信号典型传输延时为77 ns,脉冲宽度失真为2 ns。 Aiming at conventional gate drive circuits facing a series of disadvantages such as long propagation delay and low common mode transient immunity(CMTI)caused by increasing switching frequency and operating voltage level of power semiconductor devices,a capacitive-isolated gate drive circuit is designed.The drive ciruit is divided into two parts:which are low-voltage side emitter and high-voltage side receiver.A pre-amp structure is proposed to enhance the noise immunity of the gate drive circuit.An improved envelope demodulation structure is proposed to reduce the pulse width distortion after signal demodulation.The post-simulation results show that the gate drive circuit has a high CMTI capacity of 100 kV/μs,a typical signal propagation delay of 77 ns and a pulse width distortion of 2 ns.
作者 黄晓义 刘天天 赵一泽 俞跃辉 程新红 HUANG Xiaoyi;LIU Tiantian;ZHAO Yize;YU Yuehui;CHENG Xinhong(State Key Laboratory of Functional Materials for Informatics,Shanghai Institute of MicroSystem and Information Technology,Chinese Academy of Sciences,Shanghai 200050,China;Materials Science and Optoelectronic Engineering Center,University of Chinese Academy of Sciences,Beijing 100049,China)
出处 《传感器与微系统》 CSCD 北大核心 2023年第2期76-79,共4页 Transducer and Microsystem Technologies
基金 国家自然科学基金资助项目(12075307) 上海市科技创新行动计划资助项目(19511107400)。
关键词 电容隔离 栅极驱动电路 开关键控调制 共模瞬态抑制能力 脉冲宽度失真 capacitive isolation gate drive circuit on-off keying(OOK)modulation common mode transient immunity(CMTI) pulse width distortion
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