摘要
设计了一种桥式并-串联级联结构的高线性度、超宽带采样/保持电路。该采样/保持电路包括输入缓冲器、辅助开关和SEF开关三个单元。采用桥式并-串联级联结构改进的辅助开关模块单元,大幅提高了电路的线性度和带宽。该采样保持电路基于0.13μm SiGe双极型工艺进行设计,-4.75 V和2 V双电源电压供电。仿真结果表明,在100 fF采样电容、6.25 GHz采样频率、10.28 GHz输入频率的条件下,SFDR为69.60 dB,THD为-65.25 dB,-3 dB带宽达35.43 GHz。
A high linearity and ultra-bandwidth sample/hold circuit with bridge shunt-series cascade structure. The sample/hold circuit included three units, such as input buffer, auxiliary switch and SEF switch. The improved auxiliary switch module unit with bridge shunt-series cascade structure greatly improved the linearity and bandwidth of the circuit. The sample/hold circuit was designed in a 0.13 μm SiGe bipolar process, and it was powered by-4.75 V and 2 V dual supply voltage. The simulation results showed that SFDR was 69.60 dB, THD was-65.25 dB, and-3 dB bandwidth was 35.43 GHz under the conditions of 100 fF sampling capacitance, 6.25 GHz sampling frequency and 10.28 GHz input frequency.
作者
梁宏玉
王妍
李儒章
LIANG Hongyu;WANG Yan;LI Ruzhang(College of Optoelec.Engineer.,Chongqing Univ.of Posts and Telecommun.,Chongqing 400065,P.R.China;National Laboratory of Science and Technology on Analog Integrated Circuit,Chongqing 400060,P.R.China;The 24th Research Institute of China Electronics Technology Corporation.,Chongqing 400060,P.R.China)
出处
《微电子学》
CAS
北大核心
2022年第2期283-288,共6页
Microelectronics
基金
模拟集成电路国家级重点实验室基金资助项目(6142802190101)。
