摘要
为了能够在硬件上有效减少整像素运动估计(IME)的计算复杂度,提出一种基于并行螺旋搜索算法的整像素运动估计硬件架构设计方案.该设计按照螺旋顺序,首先,由中心向四周扩散的方式逐点搜索;其次,在搜索过程中每一个搜索点处同时处理所有PU块,通过这种PU块共享搜索过程的方式来减少周期数;最后,通过提前结束判断的方式,跳过不必要的搜索点,进一步减少周期数.用Verilog语言进行硬件描述,利用VCS工具进行仿真,且仿真SAD结果与HEVC参考软件(HM)结果数据一致,证明其正确性;通过对多个序列进行测试,平均每1733.4个时钟处理一个64 px×64 px大小的CTU.硬件框架在VIVADO平台下,用Virtex-7系列芯片进行综合,得到工作频率为198 MHz,能够实现4 K@56.4 f·s^(-1)的吞吐率.
In order to effectively reduce the computational complexity of integer pixel motion estimation(IME)on hardware,this paper proposes a hardware architecture design scheme of IME based on parallel spiral search algorithm.This design searches point by point in a spiral order,spreading from the center to the periphery.Secondly,all PU blocks are processed at each search point in the search process,and the number of cycles is reduced by this way of PU blocks sharing the search process.Finally,by ending the judgment early,unnecessary search points are skipped,and the number of cycles is further reduced.The hardware of this paper is described in Verilog language,and the simulation is performed using VCS tools,and the simulation results(SAD)are consistent with the results of HEVC reference software(HM),which proves its correctness.By testing multiple sequences,a 64 px×64 px CTU is processed on average every 1733.4 clocks.The hardware framework of this paper is synthesized under the VIVADO platform with Virtex-7 series chips,and the operating frequency is 198 MHz,which can achieve a throughput rate of 4 K@56.4 f·s^(-1).
作者
张志勇
施隆照
杨小玲
罗隆
ZHANG Zhiyong;SHI Longzhao;YANG Xiaoling;LUO Long(College of Physics and Information Engineering,Fuzhou University,Fuzhou,Fujian 350108,China)
出处
《福州大学学报（自然科学版）》
CAS
北大核心
2022年第1期31-38,共8页
Journal of Fuzhou University(Natural Science Edition)
基金
福建省自然科学基金资助项目(2018J01801)。
关键词
视频编码
HEVC
整像素运动估计
并行螺旋搜索
video coding
HEVC
integer motion estimation
parallel spiral search algorithm
