摘要
阐述一种采用SAR ADC作为多位量化器的三阶离散时间(DT)Sigma delta ADC调制器,在该调制器中,量化器由4位SAR ADC构成,相比于传统Flash ADC类型的量化器,减少了比较器的个数的同时,降低了调制器整体功耗。调制器结构选择单环CIFF结构兼顾了电路的精度和稳定性,电路总体采用分级结构实现,在第一级积分器中加入斩波稳定技术,消除低频噪声的干扰。提出的离散型Sigma delta ADC调制器采用TSMC 0.18μm CMOS工艺设计,在20kHz带宽实现了104.9dB的峰值信噪谐波失真比(SNDR),功耗为5.98mW,有效位数(ENOB)为17.13位。
This paper proposes a third-order discrete-time(DT) sigma delta ADC modulator using a SAR ADC as a multi-bit quantizer. In this modulator, the quantizer is composed of a 4-bit SAR ADC. Compared with the traditional Flash ADC type of quantization It reduces the number of comparators and reduces the overall power consumption of the modulator. The single-loop CIFF structure of the modulator is selected to take into account the accuracy and stability of the circuit. The circuit is generally implemented by a hierarchical structure. The chopper stabilization technology is added to the firststage integrator to eliminate the interference of low-frequency noise. The proposed discrete sigma delta ADC modulator is designed in TSMC 0.18μm CMOS process, and achieves a peak signal-to-noise harmonic distortion ratio(SNDR) of 104.9 d B in a 20 k Hz bandwidth with a power consumption of 5.98 m W and an effective number of bits(ENOB) of 17.13 bits.
作者
姜阔
刘云涛
JIANG Kuo;LIU Yuntao(School of Information and Communication Engineering,Harbin Engineering University,Heilongjiang 150001,China)
出处
《电子技术（上海）》
2022年第2期1-4,共4页
Electronic Technology
基金
黑龙江省自然科学基金项目(JJ2018ZR1021)。
