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一种面向嵌入式图形处理器的访存子系统结构设计

An architecture design of memory access subsystem for embedded graphics processor
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摘要 嵌入式图形处理器(GPU)随着访存数据量越来越大,访存子系统在性能、面积及功耗等方面的瓶颈已经日益凸显。针对图形处理器的数据特点及访存需求,考虑到嵌入式图形处理器面积及功耗的约束,结合Godson GPU架构平台,提出了一种面向嵌入式图形处理器的访存子系统结构设计。该设计主要针对图形处理流水线的访存特点,对cache的结构进行了优化,并提出了一种基于链表方式的结构,提高了访存的效率,减少了面积且降低了功耗。为了使访存子系统适配并行图形流水线,提出了一种屏幕分区方法,可以在消除cache的一致性问题的同时,使访存子系统的负载更加均衡。该设计为嵌入式图形处理器的访存子系统设计提供了借鉴。 With the increasing amount of memory access for embedded graphics processoring units(GPU),the bottleneck of the memory access subsystem in terms of performance,area and power consumption has become increasingly prominent.In view of the data characteristics and memory access requirements of the graphics processor,considering the constraints of the area and power consumption of the embedded graphics processors,combined with Godson graphic processing unit(GSGPU)architecture platform,a subsystem architecture design of memory access oriented to the embedded graphics processor is proposed.The design mainly aims at the memory access characteristics of the graphics processing pipeline,optimizes the architecture of the cache,and proposes a architecture based on the chainform method,which improves the efficiency of memory access,reduces area and power consumption.In order to adapt the memory fetching subsystem to the parallel graphics pipeline,a screen partition method is proposed,which can eliminate the cache consistency problem while making the load of the memory fetching subsystem more balanced.This design provides a reference for the design of the memory access subsystem of the embedded graphics processor.
作者 赵士彭 张立志 章隆兵 ZHAO Shipeng;ZHANG Lizhi;ZHANG Longbing(State Key Laboratory of Computer Architecture,Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;Institute of Computing Technology,Chinese Academy of Sciences,Beijing 100190;University of Chinese Academy of Sciences,Beijing 100049)
出处 《高技术通讯》 CAS 2022年第2期152-160,共9页 Chinese High Technology Letters
基金 国家自然科学基金(61521092,61432016) 中国科学院重点部署(ZDRW-XH-2017-1)资助项目。
关键词 图形处理器(GPU) 访存子系统 嵌入式处理器 链表设计 graphic processoing unit(GPU) memory access subsystem embedded processor chain form
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  • 1王鹏,伊鹏,金德鹏,曾烈光.基于三级存储阵列缓存高速数据包及性能分析[J].软件学报,2005,16(12):2181-2189. 被引量:8
  • 2蔡士杰,宋继强,蔡敏.计算机图形学[M].第3版.北京:电子工业出版社,2007:10-21. 被引量:3
  • 3Wolf W. High performance embedded computing architectu- res, applications, and methodologies [ M ]. New York : Elsevier, 2007. 被引量:1
  • 4Yoo Hoi-Jun,Woo Jeong-Ho. Mobile 3D graphics SoC from algorithm to chip [ M ]. Republic of Korea:John Wiley & Sons (Asia) Pie Lid,2009,. 被引量:1
  • 5Lindholm E, Nickolls J, Oberman S, et al. NVIDIA Tesla : a u- nified graphics and computing architecture [ J ]. IEEE Micro, 2008,28 (2) :39-55. 被引量:1
  • 6Martin M. Token coherence [D]. Wisconsin : University of Wisconsin-Madison, 2003. 被引量:1
  • 7Johansson M. General purpose computing on graphics process- ing units using OpenCL[ D ]. Sweden: Chalmers University of Technology ,2010. 被引量:1
  • 8Woo R, Choi S, Sohn Ju-Ho, et al. A low-power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3D multimedia tenninals[J]. IEEE Journal of Solid-state Cir- cuits,2004.39(7) :1101-1109. 被引量:1
  • 9Elder G. ATI Radeon 9700:architecture and 3D performance [ C ]//Proc of ACM SIGGRAPH/Eurographics. [ s. 1. ] : ACM ,2002:86-92. 被引量:1
  • 10Gareia J, March M, Cerda L, et al. On the design of hybrid DRAM,/SRAM memory schemes for fast packet buffers [ C ]// Proc of HPSR. [ s. 1. ] : IEEE Computer Society,2004 : 15-19. 被引量:1

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