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应用于CMOS图像传感器的高速列级ADC设计

A High-speed Column-parallel ADC Design for CMOS Image Sensor
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摘要 针对CMOS图像传感器的高速化设计提出了一种列级ADC电路,其采用单斜式ADC与TDC结合的方式,通过时钟信号约束比较器输出,在量化的最后一个时钟周期内产生与电压对应的时间差值。利用TDC将该差值转换为相应的数字码并与单斜式ADC的量化结果做差,实现高精度转换的同时显著提高了ADC的量化速度。基于0.18μm CMOS工艺,完成电路的具体设计、版图实现和性能验证。在模拟电压3.3 V、数字电压1.8 V、时钟频率250 MHz、输入信号范围1.5 V的条件下,10 bit ADC的信噪失真比(SNDR)达到55.74 dB,无杂散动态范围SFDR为66.79 dB,有效转换位数达到8.9 bit,DNL不超过0.3 LSB,INL不超过0.6 LSB,列级电路功耗仅为79μW,行读出量化时间压缩至1μs。为大面阵CMOS图像传感器的帧频提升提供了一种有效的ADC设计方案。 A column level ADC circuit was proposed for the high-speed design of CMOS image sensor. Using the combination of single slope ADC and TDC,the output of the comparator was constrained by the clock signal to generate the time difference corresponded to the voltage in the last clock cycle of quantization. The difference was converted into the corresponding digital code by TDC and compared with the quantization result of single slope ADC,which not only realized high-precision conversion,but also significantly improved the quantization speed of ADC. Based on 0.18 μm CMOS process,the detail design,physical layout implementation and comprehensive verification of the circuit were completed. Under the design environment of analog voltage 3.3 V,digital voltage 1.8 V,clock frequency 250 MHz and input signal range 1.5 V,the signal-to-noise distortion ratio(SNDR)of 10 bit ADC reaches 55.74 dB,the spurious free dynamic range SFDR is 66.79 dB,the effective conversion bits reach 8.9 bit,DNL does not exceed 0.3 LSB,INL does not exceed 0.6 LSB,and the power consumption of column level circuit is only 79 μW. The line readout quantization time is compressed to 1 μs. It provides an effective ADC design scheme for the development direction of CMOS image sensor with high frame rate and large array.
作者 郭仲杰 苏昌勖 许睿明 李晨 程新齐 GUO Zhongjie;SU Changxu;XU Ruiming;LI Chen;CHENG Xinqi(School of Automation and Information Engineering,Xi'an University of Technology,Xi'an,710048,CHN)
出处 《固体电子学研究与进展》 CAS 北大核心 2022年第1期44-49,共6页 Research & Progress of SSE
基金 国家自然科学基金面上项目(62171367) 陕西省重点研发计划项目(2021GY~060) 陕西省教育厅科学研究计划资助项目(19JC029)。
关键词 模数转换器 时间数字转换器 时钟压缩转换 analog to digital converter(ADC) time to digital converter(TDC) clock compression
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