摘要
极化码已被证明是第一种能够在二进制离散无记忆信道中达到信道容量的编码方式,并且实现的复杂度低,应用前景相当广阔。由于软件方式译码受到限制,在FPGA中实现极化码的快速译码有着重要的研究价值。首先介绍了SCL译码算法,采用树形流水线架构并对其中的量化和计算单元实现进行改进,使在资源消耗及译码器处理延时方面有所改善,最后在FPGA中实现了极化码的SCL译码并进行了性能分析。实验结果表明,译码的最高频率可以达到89.51 MHz,吞吐率为39.5 Mbit/s。
Polar code has been proved to be the first capacity-achieving code in the binary discrete memoryless channels,the implementation complexity is low and application prospect is quite broad.Due to the limitation of software decoding,it is of great research value to realize fast decoding algorithm of polar codes on FPGA.First,the SCL decoding algorithm is introduced.With a pipelined tree architecture,the quantization and processing element are improved to reduce the resource consumption and processing delay.Finally,the SCL decoding of polar codes is implemented on FPGA and the performance analysis is investigated.Experimental results show that the maximum frequency of the decoder is up to 89.51 MHz,and the throughput is up to 39.5 Mbit/s.
作者
方家鑫
刘纯武
黄芝平
FANG Jiaxin;LIU Chunwu;HUANG Zhiping(School of Artificial Intelligence,National University of Defense Technology,Changsha 410000,China)
出处
《移动通信》
2021年第6期125-128,共4页
Mobile Communications
基金
国家自然科学基金项目(51575517)。
