摘要
在处理数据密集型应用时,传统冯·诺依曼计算体系架构难以兼顾低延时与低功耗.通过数据处理架构创新,存内计算技术可有效提升处理器与内存间的通信效率并克服"内存墙"性能瓶颈.提出了一种基于2T1MTJ(双晶体管单磁隧道结)单元结构的通用型STT-MRAM(自旋转移矩磁性随机存储器)存内计算方案,通过复用存取晶体管将位逻辑运算的控制前置于阵列中,并能同时兼顾MRAM常规存储功能.结合SMIC 55nm工艺与p-MTJ紧凑模型进行了CMOS/MTJ混合仿真,并与基于1T1MTJ和2T2MTJ单元结构的同类方案进行了性能对比.结果表明,由于运用了和存储单元具有相同MTJ的单一逻辑运算参考单元,2T1MTJ方案的与/或位逻辑运算正确率和单元写入正确率在不同MTJ工艺偏差、TMR(隧穿磁阻效应)偏差、温度变化、电压波动情况下,整体优于1T1MTJ方案;相比2T2MTJ方案,提出方案的写入正确率高37.1%,单元面积减半.此外,还提出一种采用双阈值晶体管的改进型2T1MTJ单元结构方案,其读写性能均优于采用相同存取晶体管的2T1MTJ方案,其中对单元写入正确率的提升达9.4%.
The traditional Von Neumann computing architecture is difficult to balance low latency and low power consumption when processing data-intensive applications.By innovating the data processing architecture and effectively improving the communication efficiency between the processor and the memory,In-memory computing technology is expected to overcome this"memory wall"problem.A general-purpose STT-MRAM based on the 2T1MTJ cell structure in-memory calculation schemeis proposed,which realizes the in-memory logic operation and MRAM memory function by accessing transistors.To evaluate the proposed scheme's performance,a CMOS/MTJ hybrid simulation was performed,which combines SMIC 55nm process with MTJ compact model,and the performance was compared with similar schemes based on 1T1MTJ and 2T2MTJ cell structures.The results show that due to the use of a single logic operation reference cell with the same MTJ as the memory cell,the accuracy of the AND/OR bit logic operation and the cell write accuracy of the 2T1MTJ scheme are better than 1T1MTJ scheme in different MTJ process deviations,TMR,temperature and VDD.Compared with the 2T2MTJ solution,the writing accuracy rate of the proposed solution is 37.1%higher,and the cell area is halved.In addition,an improved 2T1MTJ cell structure using dual-threshold transistors is proposed.Its read and write performance is better than the 2T1MTJ scheme which uses the same access transistor,and the accuracy of cell writing is improved by 9.4%.
作者
郑志强
陈俊杰
颜思岑
胡炜
王少昊
ZHENG Zhiqiang;CHEN Junjie;YAN Sicen;HU Wei;WANG Shaohao(FZU-Jinjiang Joint Institute of Microelectronics,Fuzhou University,Jinjiang 362200,China)
出处
《微电子学与计算机》
2021年第11期101-108,共8页
Microelectronics & Computer
基金
国家重点研发计划(2018YFB0407603)。
