摘要
数字电路的亚稳态现象会导致数据发生误码,同步寄存器链常常被用于降低亚稳态发生的概率.为了量化由亚稳态导致的数据误码发生概率,本文从亚稳态产生的本质出发分析了亚稳态在同步寄存器链中传递的原因;推导了考虑线延迟与逻辑门延迟影响的精确亚稳态稳定时间公式;设计了一种新亚稳态测试电路计算三种亚稳态输出结果发生的概率.在平均故障时间参数的基础上,计算了因为亚稳态而造成的同步寄存器链误码率和整个系统的误码率,给出了降低系统误码率的措施.
Metastability of digital circuits can lead to data error.Synchronous register chains are often used to reduce the probability of metastability.In order to quantify the probability of data error caused by metastable state,this paper analyzes the reason of metastable transfer in synchronous register chain according to the essence of metastable state.The precise formula of metastable stability time considering the effect of linear delay and logic gate delay is derived.A new metastable test circuit is designed to calculate the probability of occurrence of three metastable output results.Based on the mean time to failure(MTBF),the bit error rate(BER)of synchronization chain and the whole system due to metastability are calculated,and the measures to reduce the BER of the system are given.
作者
王郑毅
刘文波
代少飞
李开宇
朱鹏飞
WANG Zheng-yi;LIU Wen-bo;DAI Shao-fei;LI Kai-yu;ZHU Peng-fei(College of Automation,Nanjing University of Aeronautics and Astronautics,Nanjing 210000,China;Key Laboratory of Ministry of Industry and Information Technology of Non-destructive Testing and Monitoring Technology of High-speed Carrying Facilities,Nanjing 211006,China)
出处
《微电子学与计算机》
2021年第5期14-18,共5页
Microelectronics & Computer
基金
国家重点研发计划(2018YFB2003304)
国家自然科学基金(61871218)。
关键词
亚稳态
稳定时间
亚稳态输出状态概率测试电路
同步寄存器链
误码率
metastability
the settling time
test circuit for metastable output state of probability
synchronization chains
error rate
