摘要
芯片埋入式封装技术的难点主要集中在封装制造过程对芯片造成的一系列不利影响,如裂纹、分层、翘曲、静电等。基板埋入芯片的特殊结构,大大增加了封装工艺难度。首先根据开发过程中出现的芯片聚酰亚胺分层现象建立简化模型,其次应用ANSYS工具中的内聚力单元对界面脱粘过程进行了模拟仿真,并分析了模型的等效应力值分布。结果表明,实验聚酰亚胺材料与重布线层的结合强度无法耐受封装回流过程中的热应力。最后分析了不同材料厚度对热应力的影响,为芯片埋入式封装开发提供理论参考。
The difficulty of embedded chip packaging technology is mainly concentrated on a series of adverse effects on the dies caused by the packaging manufacturing process,such as cracks,delamination,warpage,ESD,etc.The special structure of the embedded die substrate greatly increases the difficulty of the packaging process.This research first establishes a simplified model based on the polyimide delamination phenomenon of the chip during the development process,and then uses the cohesive unit in the ANSYS tool to simulate the interface de-bonding process,and analyzes the equivalent stress value distribution of the model.The results show that the PI-RDL material cannot withstand the thermal stress during the package reflow process.Finally,the influence of different material thicknesses on thermal stress is analyzed,which provides a theoretical reference for the development of embedded chip packaging.
作者
吴昊平
周青云
胡滢
WU Haoping;ZHOU Qingyun;HU Ying(JCET Group Co.,Ltd.,R&D Center,Wuxi 214432,China)
出处
《电子与封装》
2021年第4期36-41,共6页
Electronics & Packaging
