摘要
本文主要介绍了数字频率合成器的原理,针对系统中出现的时间失配问题,分析提出了一种DDS优化设计,主要从硬件以及软件角度介绍该装置,重点分析了基于FPGA建立时间检测器,来消除由于DDS的ioupdata信号不稳定导致其产生相位抖动。该设计具有软件化,模块化,且易于调整和扩展的优点;经过在整机上验证,采用此种方法设计达到了较为理想的性能指标。文章最后给出了逻辑实现电路和试验结果,通过试验验证该设计在技术上具有可行性,DDS的ioupdata信号稳定性好,有较高的实用价值。
This paper describes the principle of the direct digital frequency synthesizer(DDS)at first,analyzes the time mismatch problem in the DDS,and then proposes an optimized DDS.The optimized DDS is mainly described from the perspective of hardware and software.The FPGA-based time detector is described in detail which eliminates the phase jitter caused by the unstable ioupdata signals of the DDS.The optimized DDS features softwarization,modularization,and easy adjustment and extension.System level test results show that the optimized DDS has good performance specifications.Finally,the logic implementation circuit and test results are provided.The optimized DDS has high practical value because it is technically feasible and its ioupdata signals have high stability.
作者
胡思雨
关炀
HU Siyu;GUAN Yang(No.20 Research Institute of CETC, Xi'an 710068)
出处
《火控雷达技术》
2020年第3期42-46,共5页
Fire Control Radar Technology
