摘要
由于半导体芯片设计已经到了纳米量级,单位面积内的标准单元越来越密集。这个可以不断提升芯片的集成度,但同时也让单位面积内的电流密度或者说单位面积的功耗密度不断增加。这就需要数字后端工程师需要在电路设计中考虑电源网络和功耗问题,目的是不要出现过大的压降。目前行业内对最终电压降的违例大多是通过手动修复的方式。这种方式的效率非常低。布局布线工具如cadence的innovus也提供了自动修复的流程。但是默认流程的修复效果不能在最终的签核(signoff)工具中得到验证。这是由于行业内大多设计公司采用了Synopsys的Starrc和PrimeTime作为signoff的工具。而这两个工具对RC参数和时序的算法与Cadence的工具不一致。这就会造成innovus内部看到的电压降情况与voltus signoff的不一致。从而达不到针对性的修复。本文基于行业内流行的跨平台数字后端流程,将signoff阶段的RC和时序数据加载到innovus当中,让innovus看到了和signoff同样的电压降情况,从而做到了自动又高效的电压降违例修复。
As semi-conductor chip design now is in nm level,there are more and more standard cells in unit area.This will increase integration density of chips.But it makes current density or power density higher and higher in unit area meanwhile.This requires P&R designers to consider power network and power distribution to make sure not too large IR drop.However,when we finish our designs,we must fix IR drop violations manually in current industry,which is a very low efficient way.PR tools as Innovus of cadence provides automatic fix flow.But fixed violations of default flow usually cannot be verified by signoff tool Voltus.This is because most of companies of industry use Starrc and PrimeTime of Synopsys as signoff tools.These two tools do different calculation for RC parameters and timing.This will make different IR drop between Innovus and Voltus as signoff tools,which is the root cause of none focus fixing.This paper based on popular multi-tools PR flow of current industry,load RC and timing data of signoff stage into Innovus,make exactly same IR drop report between Innovus and Voltus.Thus,we get an efficient automatic method of IR drop violation fix in multi-tools PR flow.
作者
余金金
YU Jin-jin(Enflame tech)
出处
《中国集成电路》
2020年第7期29-34,共6页
China lntegrated Circuit
