摘要
如何选择满足建模精度要求的最小字长与仿真步长是电力电子系统实时仿真模型在FPGA(field programmable gate array)实现时的难点问题之一。首先,提出了一种电力电子实时仿真建模FPGA资源优化方法,该方法基于信噪比理论,通过计算变量字长、仿真步长与模型精度的关系确定满足建模精度要求的最小字长和步长,以此来达到优化FPGA资源的效果;然后,以基于LC滤波的三相逆变器系统为例,采用ADC(associated discrete circuit)的方法进行实时仿真建模并计算其信噪比,离线仿真验证了输出字长25位,仿真步长100 ns是满足模型精度的最小字长和最佳步长;最后,硬件在回路仿真实验和实物实验分别验证了FPGA的资源优化效果和建模理论的正确性。
It is one of the most important projects to choose the minimum bit-length and optimal time step which meet model accuracy when real-time simulation model of power electronics is implemented in FPGA.Based on the concept of SNR(signal-noise ratio),a FPGA resource optimization method was proposed for power electronics real-time simulation modeling.The quantitative relationship among time step,bit-length and model accuracy was calculated to choose the minimum bit-length and optimal time step,which can optimize FPGA resource occupation.In addition,taking a three-phase inverter with LC filter for example,ADC(associated discrete circuit)modeling method was used for real-time simulation modeling and the SNR was calculated.Offline simulation verifies that the bit-length for 25 bits and the time step for 100 ns are the minimum bit-length and optimal time step that meet the model accuracy.Finally,hardware-in-the-loop(HIL)simulation and real experiments verify the effect of FPGA resource optimization and the validity of modeling method respectively.
作者
郭希铮
袁佳琦
游小杰
张子钰
GUO Xi-zheng;YUAN Jia-qi;YOU Xiao-jie;ZHANG Zi-yu(School of Electrical Engineering,BeijingJiaotong University,Beijing,100044,China)
出处
《电机与控制学报》
EI
CSCD
北大核心
2020年第7期12-19,共8页
Electric Machines and Control
基金
国家重点研发计划(2016YFE0131700)。
关键词
实时仿真
FPGA
资源优化
字长
仿真步长
信噪比
real-time simulation
field programmable gate array
resource optimization
bit-length
time step
signal-noise ratio
