基于HEVC帧内硬件编码器的架构及算法

Hardware Architecture and Algorithm Based on HEVC Intra Encoder

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摘要针对战场视频情报的编解码,提出了一种基于HEVC标准的帧内编码器的硬件结构及算法实现,支持分辨率为2160@30fps视频的实时帧内编码操作。编码器基于码域的bin计数和基于变换域的失真估计简化率失真分析,可以对大量帧内预测模式进行筛选。同时建立单独的4×4块重构回路,以支持帧内4×4模式;不同尺寸的块交叉处理以补偿重构回路的延时。编码器的实现使用了TSMC-90 nm芯片的1086 k门以及52 kB片上内存。在2160p@30fps视频序列下,相比于HM软件,BD-Rate均值为5.46%。 For battlefield video,the paper presents the algorithm and its hardware architecture able to support the intra encoding up to the 2160p@30fps resolution.The rate estimation based on bin counting and the distortion estimation in the transform domain simplify the rate-distortion analysis and enable the evaluation of a great number of candidate intra modes.The processing of blocks with different sizes is interleaved to compensate the delay of reconstruction loops.To support intra 4×4 modes,the encoder incorporates a separate reconstruction loop.The encoder utilizes 1086 k gates and 52 kB on-chip memories for TSMC 90 nm.For 2160p@30fps videos,the average BD-Rate is 5.46%.

作者张晓宁王克谭伟峰习朝辉张志峰 ZHANG Xiao-ning;WANG Ke;TAN Wei-feng;XI Zhao-hui;ZHANG Zhi-feng(North Automatic Control Technology Institute,Taiyuan 030006,China)

机构地区北方自动控制技术研究所

出处《火力与指挥控制》 CSCD 北大核心 2020年第3期156-161,166,共7页 Fire Control & Command Control

关键词视频情报视频编码帧内预测 HEVC FPGA 时序 video intelligence video coding intra prediction HEVC FPGA scheduling

分类号 TN929 [电子电信—通信与信息系统]