摘要
为了提高集成电路抗逆向工程的能力,通过对逻辑混淆技术的研究,提出了一种基于Reed-Muller伪装门的逻辑混淆设计方案。该方案首先在同一版图上采用不同虚拟孔配置实现基本单元异或门/与门逻辑功能,并提取逻辑混淆单元的特征信息制作标准单元库;然后利用随机插入算法将混淆标准单元电路应用于电路网表;最后采用基准电路验证所提方案的有效性。仿真结果显示,Reed-Muller逻辑伪装门比标准单元库的版图相似度提高了14.36%,而较大规模测试电路功耗额外开销仅为2.36%。仿真结果表明,所设计的伪装门可以有效地防御逆向工程,提高了电路的硬件安全。
To improve the ability of the integrated circuit to resist reverse engineering,we study the logic obfuscation technology and propose a logic obfuscation scheme based on the Reed-Muller camouflage gate.First,different virtual hole configurations are adopted to realize XOR/AND logical functions on the same layout,and feature information of the logical obfuscating circuit is extracted to make the standard cell physical library.Then,the obfuscation physical library is applied in the circuit netlist by the random insertion algorithm.Finally,the ISCAS benchmark is used to verify the effectiveness of the proposed scheme.Simulation results reveal that the similarity of the Reed-Muller logic camouflage layout is improved by 14.36%,and that the power consumption overhead is about 2.36% under the larger scale benchmark.Experiment indicates that the designed obfuscation gate can effectively resist reverse engineering and improve the hardware security of the circuit.
作者
吴秋丰
张跃军
汪鹏君
张会红
WU Qiufeng;ZHANG Yuejun;WANG Pengjun;ZHANG Huihong(School of Information Science and Engineering,Ningbo University,Ningbo 315211,China;College of Electrical and Electronic Engineering,Wenzhou University,Wenzhou 325035,China)
出处
《西安电子科技大学学报》
EI
CAS
CSCD
北大核心
2020年第2期135-141,共7页
Journal of Xidian University
基金
国家自然科学基金(61871244,61874078)
浙江省自然科学基金(LY18F040002)
浙江省大学生新苗人才计划(2019R405072)
宁波大学学生科研创新项目(2019SRIP1311)
宁波大学王宽诚幸福基金
宁波大学孔爱菊教育基金。
