摘要
为了提高时序电路等价性验证速度,提出了一种并行的验证方法。时序电路就是一种有限状态机,本文借鉴有限状态机的并行最简化方法来设计一种并行的时序电路等价性验证方法,并以实例证明了该方法的有效性和可行性。
In order to improve the speed of equivalence verification of sequential circuits,a parallel verification method is pro posed.Sequential circuit is a finite-state machine.This paper designs a parallel method for verifying equivalence of sequential cir cuit by using the parallel simplified method of the finite-state machine,and proves the effectiveness and feasibility of this method with examples.
作者
张留宛
ZHANG Liu-wan(Changzhou Vocational Institute of Engineering,Changzhou 213164,China)
出处
《电脑知识与技术》
2019年第10Z期235-237,共3页
Computer Knowledge and Technology
关键词
时序电路
有限状态机
等价性
sequential circuit
finite-state machine
equivalence
