摘要
随着数据Cache容量不断的增大,制造工艺不断的进步,存储单元尺寸不断的缩小,位线不断的变长,数据的访存时间也将随之不断地变长。为了提高数据Cache的访存速度,就必须在数据传输的关键路径上减小其延迟时间,一种比较实用的措施就是在位线与其输出单元间设置灵敏放大器(Sense Amplifier,SA),以此降低位线电压的波动,进而达到加快数据Cache访存速度的目的,因此灵敏放大器是数据Cache的关键部件之一,它在整个数据Cache电路的功能、性能和可靠性方面起着不可忽视的作用。论文论述了新工艺下一款容偏差灵敏放大器的研究与实现,并对该结构进行了同类比较和可靠性分析。该结构采用全定制设计,最高频率可达到2.5GHz,单独工作自身差分电压达到20mv。
With the incessant increase of data Cache capacity,the continuous advancement of manufacturing process,the growing of bit line,and data access time also continues to grow.In order to increase the speed of data Cache access,it is necessary to reduce the time on the critical path of data transmission.One more practical measure is to set a Sense Amplifier(SA)between the bit line and its output unit to reduce the fluctuation of the bit line voltage,thereby achieving the purpose of speeding up the data cache access.Therefore,the sense amplifier is one of the key components of the data cache,and it plays an important role in the function,performance and reliability of the entire data Cache circuit.This paper discusses the research and implementation of a tolerance deviation sense amplifier under new process,and carries out similar comparison and reliability analysis of the structure.This structure is fully custom designed,with a maximum frequency can achieve 2.5 GHz and differential voltage attains 20 mv for individual operation.
作者
张立
姚荣
方华
ZHANG Li;YAO Rong;FANG Huan(Shanghai Hi-performance IC Design Center,Shanghai 201204)
出处
《计算机与数字工程》
2019年第11期2667-2670,共4页
Computer & Digital Engineering
基金
核高基重大专项“国产处理器核心性能提升研究”(编号:2018ZX01029-101)资助
