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通用型芯片级光纤通信接口设计 被引量:4

The design of universal chip-level optical fiber communication interface
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摘要 为解决芯片与外部设备的海量数据实时传输的问题,本文以光纤通信技术为基础设计数据传输接口,在接口内分层搭建通信协议及交互接口架构,实现了网络各层之间的通信与校验工作.利用AXI4-Stream总线应用范围广且具有强大支持平台的优势,将AXI4-Stream接口作为芯片级数据交换接口,为突发性高速数据传输提供了支持.该接口支持UDP/IP协议封装格式,使其能灵活兼容于各类上层应用;支持通过可编程接口配置传输层端口号、IP地址及MAC地址;应用流水线技术及多进程并行处理技术,在控制面积及功耗的条件下,减少数据传输延迟,优化接口处理性能.最后通过光纤将片内数据传输到PC机进行了验证,数据传输速率可达9.691 Gbps,满足芯片与外部设备海量数据高速传输需求. In order to solve the problem of mass data transmission between chips and external devices, the interface of data transmission is designed based on the optical fiber communication technology in this paper. The communication protocols and the interactive interface architectures are bulit in the interface to realize communication and verification between layers of the network. Many IP providers support the AXI protocol and it have a robust support platform, so the AXI4-Stream interface is used as a chip-level data exchange interface to support the bursty high-speed data transmission. UDP/IP format is supported for flexible compatibility with various upper-layer applications. The number of port, IP address and address of MAC layer can be set by programmable interface. Pipeline technology and multi-process parallel processing technology are applied to reduce data transmission delay and optimize interface processing performance under the control of area and power consumption. Finally, the design is verified by transmitting data in chip to PC via fiber optic communication and the data transmission data has reached up to 9.691 Gbps. It is demonstrated that the interface is able to meet the high-speed transmission requirement of massive data between chips and external devices.
作者 许川佩 刘华颖 XU Chuan-pei;LIU Hua-ying(Guangxi Key Laboratory of Automatic Detection Technology and Instrument,Gulin University of Electronic Technology,Guilin 541004,China)
出处 《微电子学与计算机》 北大核心 2019年第11期24-29,共6页 Microelectronics & Computer
基金 国家自然科学基金(61671164)
关键词 光纤通信 AXI4-Sream UDP/IP协议 FPGA optical fiber communication AXI4-Sream UDP/IP protocol FPGA
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