摘要
FPGA已广泛用于卷积神经网络的硬件加速器的实现.本文设计了一种基于FPGA的卷积神经网络加速器.主要利用卷积神经网络中固有的并行性来减少实时嵌入式应用所需带宽与资源使用,并将其在有限资源的ZC706开发板上实现,结果显示,在150 MHz的工作频率下,FPGA的峰值运算速度达到0.54 GOP/s,且功耗很小.
FPGAs are widely used in the implementation of hardware accelerators for convolutional neural networks. This paper designs a FPGA-based CNN acceleration structure. It mainly utilizes the inherent parallelism in CNN to reduce the bandwidth and resource usage required by real-time embedded applications, and implements it on the ZC706 development board with limited resources. The results show that the FPGA operates at a frequency of 0. 54 GOP/s and consumes very little power at 150 MHz.
作者
翟社平
邱程
杨媛媛
李婧
江婷婷
ZHAI Shaping;QIU Cheng;YANG Yuan-yuan;LI Jing;JIANG Ting-ting(School of Computer Science and Technology,Xi'an University of Posts and Telecommunications,Shaanxi Key Laboratory of Network Data Analysis and Intelligent Processing,Xi'an 710121,China)
出处
《微电子学与计算机》
北大核心
2019年第8期83-86,共4页
Microelectronics & Computer
基金
工业和信息化部通信软科学项目(2018-R-26)
陕西省社会科学基金(2016N008)
西安市社会科学规划基金(17X63)
西安邮电大学研究生创新基金项目(CXJJ2017062)
关键词
卷积神经网络
现场可编程门阵列
加速器
有限资源
convolutional neural network
field-programmable gate array
accelerator
limited resources
