摘要
为了进一步提高Montgomery模乘的效率,对通用Montgomery模乘算法进行改进,提出一种在单位时钟内能可变步长迭代计算模乘的方案。并结合硬件结构特点设计串并混合结构的模乘运算电路,通过modelsime10.2a及Synplify Pro工具分别进行仿真验证和综合测试。在Xilinx Virtex2系列的xc2v3000 FPGA芯片中综合结果表明,当选取步长为13时,执行一次163位的模乘运算仅需43ns,此时最高频率可达304MHz;当选取步长为14时,完成一次233位模乘仅需要17个时钟周期,且取得速度与资源取的最佳折衷。
In order to further improve the efficiency of Montgomery modular multiplication,the general Montgomery modular multiplication algorithm is improved.This paper proposed an iterative computation of modular multiplication with variable step size in the unit clock.Combining with the characteristics of hardware structure,we designed a modular multiplication circuit of the serial and parallel mixed modular multiplication circuit.The simulation verification and comprehensive test were performed separately by modelsime 10.2a and Synplify Pro.The results of running on Xilinx Virtex2 xc2v3000 FPGA chips show that when the step size is 13,only 43 ns is needed to perform a 163-bit modular multiplication operation,and the highest frequency can reach 304 MHz.When the step size is 14,only 17 clock cycles are needed to complete a 233-bit modular multiplication,and the best compromise between speed and resource is obtained.
作者
张丽
董秀则
明娇娇
高献伟
Zhang Li;Dong Xiuze;Ming Jiaojiao;Gao Xianwei(School of Communication Engineering, Xidian University, Xi'an 710071, Shaanxi, China;Department of Electronic, Beijing Electronics Science and Technology Institute, Beijing 100070, China)
出处
《计算机应用与软件》
北大核心
2019年第6期292-295,326,共5页
Computer Applications and Software
基金
国家自然科学基金项目(61701008)
