摘要
将空气隙应用于逻辑器件后段金属互连线中可以有效降低互连线间的寄生电容,提升电路信号传输速度,但制备过程仍具有一定的困难。基于三维闪存(3D NAND)中后段(BEOL)W的自对准双重图形化(SADP)工艺,利用湿法刻蚀的方法在W化学机械平坦化(CMP)之后去除SiO_2介质层,然后再利用化学气相淀积(CVD)法淀积一层台阶覆盖率较低的介质在金属互连线层内形成空气隙。采用空气隙结构代替原来的SiO_2介质层可降低约37.4%的寄生电容,且薄膜的台阶覆盖率会进一步降低电容。TCAD仿真和电性能测试结果表明,采用该方法制备的空气隙结构可降低互连延迟。
The application of air-gap to the back-end metal interconnect of the logic devices can effectively reduce the parasitic capacitance between interconnects and improve signal transmission speeds of circuits. But the manufacture process has many difficulties. Based on the W self-aligned double patterning(SADP) process of the back-end-of-line(BEOL)of 3 D NAND flash, the wet etching method was used to remove the SiO2 dielectric layer after W chemical mechanical planarization(CMP). Then the chemical vapor deposition(CVD) method was used to deposit a dielectric film with low step coverage to form an air-gap within the metal interconnect layer. Using air-gap instead of the original SiO2 dielectric layer can achieve a 37.4% reduction in parasitic capacitance, and the step coverage of the film further affects the capacitance reduction. The TCAD simulation and electrical test results show that the interconnect delay can be reduced effectively by the air-gap structure prepared with this rnethod.
作者
袁璐月
刘峻
范鲁明
郭安乾
夏志良
霍宗亮
Yuan Luyue;Liu Jun;Fan Luming;Guo Anqian;Xia Zhiliang;Huo Zongliang(School of Microelectronics, University of Chinese Academy of Sciences , Beijing 100049, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Yangtze Memory Technologies Co. , Ltd. , Wuhan 430205 , China)
出处
《半导体技术》
CAS
北大核心
2019年第4期281-285,共5页
Semiconductor Technology
基金
国家自然科学基金资助项目(61474137)
关键词
三维闪存
W互连
RC延迟
空气隙
低台阶覆盖率
3D NAND flash
W interconnection
RC delay
air-gap
low step coverage rate
