摘要
铁电负电容晶体管的亚阈值斜率可低于60 mV/dec的理论极限,是未来突破晶体管工作电压VDD和器件尺寸进一步减小瓶颈的关键。自2008年低功耗负电容晶体管的概念被提出以来,该晶体管因简单的器件结构和优异的电路性能而一直受到业界学者的广泛关注。然而,这种基于具有负电容特性铁电材料的晶体管的缺点也日渐凸显,特别是负电容的不稳定性对该晶体管的应用造成严重阻碍。相比传统晶体管,负电容晶体管应用于低功耗电路具有两大优势:(1)亚阈值斜率可低于60 mV/dec,降低电路工作电压的同时开关电流比不会下降,静态泄露电流不增加;(2)器件尺寸更小,减小电路面积。然而,负电容晶体管由于铁电材料的滞回特性,在开关电路中具有严重的滞回现象,导致电路逻辑紊乱,无法正常工作。不仅如此,负电容成因的复杂性也使其建模非常困难。因此,近十年来除研究铁电材料种类和参数对器件性能的影响外,研究者们还整理出了决定滞回现象的关键因素,并提出了有效抑制滞回现象的方法。目前,通过调整铁电负电容和晶体管电容的比例,滞回窗口已经可以减小到近乎为零。而与实验图形较吻合的负电容数学模型直到2017年才出现,但模型中的数据还没有科学的测定方法,目前还处于发展完善阶段,仍需要大量的研究和探索。负电容晶体管制备过程简单,工艺和标准CMOS工艺兼容,基底MOSFET制作完成后,将具有负电容特性的铁电材料沉积在栅上形成叠栅。负电容晶体管制作的难点在于稳固铁电和氧化物界面、减少缺陷空位。目前,国内外已出现流片成功的负电容晶体管,成品测试的最小亚阈值斜率可达16 mV/dec,但滞回现象出现的概率非常大,并且在提高器件的疲劳性和稳定可靠性方面还需要投入更多的研究。使用频率较高的负电容材料有PbZrTiO3(PZT)、SrBi2Ta2O9(SBT)、P(VDF-T
It is possible for ferroelectric negative capacitance transistor to make the sub-threshold swing lower than the theoretical limit of 60 mV/dec,which is the key to break through the bottleneck of reducing working voltage V DD and device size in the future.Since the concept of low power consumption negative capacitance transistor was proposed in 2008,this kind of transistor has been attracting numerous attention from researchers thanks to its simple device structure and excellent circuit performance.Nevertheless,the weakness of the transistor that based on ferroelectric materials with negative capacitance characteristics are becoming increasingly prominent,particularly,the instability of negative capacitance.It must be a serious block for the application of the transistor.Compared with conventional transistors,negative capacitance transistors exhibit two great advantages when applied to low-power circuits.First,the sub-threshold slope can be lower than 60 mV/dec,and there will be no decline in switching current ratio and no increase in static leakage current while the circuit operating voltage is reduced.Second,the device size can be smaller which contribute to the reduction of circuit area.However,due to the hysteresis characteristic of ferroelectric materials,the negative capacitance transistor show serious hysteresis in switching circuit,leading to the disorder of logic circuit and abnormal working situation.Besides,the complexity of the cause of negative capacitance makes it quite difficult to be modeled.Hence,in recent 10 years,in addition to studying the effects of ferroelectric material and its parameters on device performance,the researchers have also put great efforts in sorting out the key factors that dominate the hysteresis phenomenon,and proposed several effective methods to suppress hysteresis phenomenon.At present,hysteresis window can approach to zero through adjusting the proportion of negative capacitance and transistor capacitance.The mathematical model of negative capacitance,which was in good a
作者
谭欣
翟亚红
TAN Xin;ZHAI Yahong(School of Micro-Electronics and Solid-State Electronics,University of Electronic Science and Technology of China,Chengdu 610054)
出处
《材料导报》
EI
CAS
CSCD
北大核心
2019年第3期433-437,共5页
Materials Reports
基金
电子元器件可靠性物理及其应用技术重点实验室开放基金(ZHD201601)
中央高校基本科研业务费专项资金(ZYGX2016J047)~~
关键词
铁电
负电容
负电容晶体管(NCFET)
低功耗
ferroelectric
negative capacitance
negative capacitance transistor(NCFET),low power dissipation
