摘要
为了降低极化码编码硬件电路的成本并提高编码结构的灵活性,从面积优化的角度,提出了一种基于FPGA的低硬件复杂度的极化码编码实现方案。采用复用结构替换极化码编码中硬件复杂度较高的直接并行克罗内克积运算结构,并将其封装成可以实现任意维数克罗内克积运算的IP核。实验结果表明,当基矩阵为2阶时,实现最小运算单元所需的寄存器数量降低至原来的1/4,整体硬件复杂度降低至与码长呈线性关系的复杂度。
In order to reduce the cost of the polarization code encoding hardware circuit and improve the flexibility of the coding structure,an FPGA-based implementation of low-hardware complexity polarization code coding is proposed.The direct parallel Cronoke product operation structure with high hardware complexity in the polarization code coding is replaced by a multiplexing structure,and is encapsulated into an IP core capable of realizing any dimensional Kronecker product operation.The experimental results show that when the base matrix is second-order,the number of registers required to implement the minimum arithmetic unit is reduced to 1/4,and the overall hardware complexity is reduced to a linearity with the code length.
作者
周秉毅
陈紫强
谢跃雷
黄志成
ZHOU Bingyi;CHEN Ziqiang;XIE Yuelei;HUANG zhicheng(Ministry of Education Key Laboratory of Coginitive Radio and Information Processing,Guilin University of Electronic Technology,Guilin 541004,China)
出处
《桂林电子科技大学学报》
2018年第6期448-452,共5页
Journal of Guilin University of Electronic Technology
基金
国家自然科学基金(61461015)
桂林电子科技大学研究生教育创新计划(2017YJCX24)
