摘要
自Turbo编码问世以来,为了实现较低复杂度和优良比特误码率(BER)性能的Turbo译码器,已经有多种简化的对数最大后验概率(Log-MAP)算法被提出。针对Log-MAP算法,提出了一种基于组合逻辑电路(CLC)的复杂度很低的硬件实现架构。该CLC架构可以应用于所有现有的简化Log-MAP算法,只需将其中用于计算fc的算术模块替换为逻辑电路。通过仿真及FPGA实现验证了在相同BER性能下,使用提出的架构可以节约多达30%的硬件资源。此外,该CLC架构无需关注fc是否能用一个简单的函数描述即可硬件实现Log-MAP算法。
With the advent of turbo code,various simplified logarithmic maximum a posteriori(Log-MAP)algorithms have been proposed in order to implement a turbo decoder with lower complexity and better bit error rate(BER)performance.Aiming at Log-MAP algorithms,a hardware architecture based on combinational logic circuit(CLC)with very low complexity is proposed in this paper.The CLC algorithms can be applied to all the existing simplified Log-MAP algorithms only by replacing the arithmetic module for f_c computing module with logic circuit.The simulations and FPGA implementation results show that with the same BER performance,up to 30%hardware resources can be reduced when the proposed architecture is employed.In addition,the proposed architecture can be used to implement any correction term approximation schemes of Log-MAP algorithm without considering if the f_c can be described by a simple function to implement Log-MAP algorithm.
作者
王东
李秀朋
WANG Dong;LI Xiupeng(The 54th Research Institute of CETC,Shijiazhuang 050081,China)
出处
《无线电通信技术》
2018年第3期263-267,共5页
Radio Communications Technology
