摘要
为了提高基于FPGA平台的SoC设计方案的开发速度和运行性能,提出一种基于高层次代码转换的高级综合优化方法.首先将高级语言算法进行软硬件划分,确定在硬件上执行的部分;然后针对在硬件上执行的算法部分,通过代码转换去除函数间数据依赖性、提高循环体并行性,并对循环体进行流水线化;最后将优化方法应用到Alpha-beta搜索算法,完成Blokus-Duo设计.实验结果表明,该方法将高级语言描述自动转化为适于高级综合工具优化的代码模式,提高高级综合生成电路的性能,优化后高级综合生成电路的速度比优化前提高了14倍.
To improve the performance of the SoC based on FPGA designs and reduce the time to market,thispaper pro-poses an optimization approach for high-level synthesis based on the transformation of the high-levelcodes.Firstly,hardware and software partition of the high-level algorithm is explored to determine which partwill be executed on the FPGA.Secondly,in allusion to hardware partition,approaches are applied to remove thedata dependency between different functions,improve the parallelism of the loops and pipeline the loop body.Finally,the proposed method is applied to the Alpha-beta searching algorithm,which is used for designingBlokus-Duo game player.The experimental results show that the high-level codes can be transformedautomatically to the appropriate pattern which is fit for the high-level synthesis to improve the performance.Incomparison with the hardware implementation without code transformation,the proposed optimization methodimproves the running speed by14times.
作者
马磊
刘强
徐松
Ma Lei;Liu Qiang;Xu Song(Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology, School of Microelectronics, Tianjin University, Tianjin 300072)
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2017年第7期1372-1379,共8页
Journal of Computer-Aided Design & Computer Graphics
基金
国家自然科学基金(61574099)
关键词
高级综合
可编程门阵列
硬件加速
代码转换
high-level synthesis
FPGA
hardware acceleration
code transformation
