摘要
OFDM系统中,符号定时同步主要进行相关运算,运算量大,且实时性要求非常高,在系统资源中占据了较大比重。因此,设计了一种基于训练序列的定时同步FPGA实现结构,将转置滤波器的思想应用于滑动相关运算,可以有效缩短关键路径,降低计算时延,减少资源消耗,还可灵活配置复数乘法器的使用数量,满足各种速率的运算要求。最后,在FPGA上进行了实现和仿真测试,验证了该设计的可行性。结果表明,该结构在工程应用中具有较好的实用价值。
In OFDM system, symbol timing synchronization is a large proportion of system resources because of its large amount of computation and high real-time requirement. In this paper, a timing synchronization FPGA structure based on training sequence is designed, which applies the idea of transposed filter to sliding correlation operation. It can effectively shorten the key path, reduce the time delay and the consumption of resource. In addition, it can flexibly co requirements of various rates. Finally, simulation test on FPGA. The results nfigure the number of complex multipliers and meet the operation the feasibility of the design is verified by the implementation and show that the structure has good practical value in engineering application.
作者
杨建平
李路
郭强胜
YANG Jian-ping;LI Lu;GUO Qiang-sheng(No.30 Institute of CETC,Chengdu Sichuan 610041,China)
出处
《通信技术》
2018年第10期2314-2319,共6页
Communications Technology
