摘要
针对现场可编程逻辑门阵列(FPGA)实现BP神经网络仍存在的激活函数实现困难及输入输出吞吐量不够等几个关键性问题,采用平滑插值法对S型激活函数做进一步改进,在中间数据存储中提出采用寄存器循环缓存方式,在网络搭建中利用高效的FPGA深度流水线技术实现网络的串并联。通过上述3点技术处理,进一步提高BP神经网络的运算速度。实验数据统计分析结果表明,网络与期望输出全部样本误差均小于0.01情况下,收敛速度几近超出软件实现速度3个数量级,为人工神经网络的硬件实现提供了理论依据。
For the implementation of BP neural network by FPGA,several key issues exist such as the implementation of activation function and the throughput capacity of input and output.To solve the problem,the S activation function was improved using smoothing interpolation method.Referred to the intermediate data storage,the method of circular buffer was raised.In the network construction,the efficient FPGA deep pipelining technology was used to realize the series-parallel connection of the network.The operation speed of BP neural network was further improved by means of the three points mentioned above.On the grounds of statistical analysis of experimental data,the convergence rate is almost 3 orders of magnitude higher than the speed of software implementation under the situation that all the sample errors of the network and expected output are less than 0.01.It provides a theoretical basis for the hardware implementation of artificial neural networks.
作者
杨景明
杜韦江
吴绍坤
李良
魏立新
YANG Jing-ming1,2, DU Wei-jiang1, WU Shao-kun1 , LI Liang1 , WEI Li-xin1(1. Key Lab of Industrial Computer Control Engineering of Hebei, Yanshan University, Qinhuangdao 066004, China;2. National Engineering Research Center for Equipment and Technology of Cold Strip Rolling, Qinhuangdao 066004, Chin)
出处
《计算机工程与设计》
北大核心
2018年第6期1733-1737,1773,共6页
Computer Engineering and Design
基金
河北省自然科学基金项目(F2016203249)
河北省高等学校创新团队领军人才培育计划基金项目(LJRC013)
