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锁相接收机扫描电路数字化设计 被引量:1

Digital Design of Scanning Circuit in Phase Lock Receiver
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摘要 针对模拟扫描电路一致性差、性能随老化下降等问题,提出采用数字扫描方法实现锁相接收机辅助截获。文章从锁相接收机的原理出发,分析了最大数字扫描速率。通过锁相环扫描捕获探索试验,得到了最稳健的数字扫描速率。 The difference of analog scanning circuits is obvious.The performance of analog scanning is dropped down when device aging occur.To solve those problems,digital design method of scanning circuit is brought forward to assist phase lock receiver with intercept and capture.According to the principle of phase lock receiver,the velocity of max digital scan is analyzed.The velocity of scan is confirmed at last though the design of hardware and the explore experiments that validate scan and capture of phase lock receiver.
作者 丁亚军 成志锋 傅黎黎 陈煦 DING Ya-jun;CHENG Zhi-feng;FULi-li;CHEN Xu(China Aerospace Science and Technology Corporation, Beijing 100048, China;Shanghai Radio Equipment Research Institute, Shanghai 200090, China)
出处 《制导与引信》 2017年第4期1-4,共4页 Guidance & Fuze
关键词 锁相接收机 扫描电路 数字化设计 phase lock receiver scanning circuit digital design
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