摘要
功耗、速度和芯片面积是当今便携电子领域极为关键的技术参数.本文拟采用不同的数字逻辑技术和不同电路结构设计并实现数字逻辑比较器,使电路在功耗、传输延迟、芯片面积以及占用晶体管数等方面得到优化.基于Tanner-EDA仿真平台,选用电源电压0.7 V及45-nm工艺参数规范,对本文设计的每种电路的功耗、速度和面积进行仿真,通过分析比较仿真结果,综合每种电路的结构特点和电性能参数,选取最优电路设计,对该电路进行版图设计和版图参数提取,从而进行电路后仿真验证并最终实现高性能的数字逻辑比较器电路芯片.
The rapid integration of VLSI circuit is due to the increased use of portable wireless systems with low power budget and microprocessors with higher speed. To achieve high speed and lower power consumption transistor technology and power supply must be scaled down simultaneously. In the present scenario low power, speed and size play a significant role specifically in the field of digital VLSI circuits. The major goal of this paper is to design and implement of digital comparator using different logic techniques and compared in terms of power consumption, propagation delay and transistor count. The results of this paper are simulated on the tanner - EDA tool realized in 45 - nanometer technology at 0.7 v supply voltage.
作者
袁寿财
武华
王兴全
YUAN Shoucai, WU Hua, WANG Xingquan(School of Physics and Electronics Information, GanNan Normal University Ganzhou 341000, Chin)
出处
《赣南师范大学学报》
2018年第3期32-35,共4页
Journal of Gannan Normal University
基金
江西省科技厅基金20171BAB202037
20151BAB202019
国家自然科学基金面上项目51377025
关键词
数字逻辑比较器
传输门
半加器
功耗
传输延迟
digital logic comparator
transmission gate
half adder
power dissipation
propagation delay
