摘要
为分析导弹发射过程中采集的图像参数,需要将数据存储以便于读取回收。本文采用FPGA作为核心逻辑控制器,针对双路弹上高速LVDS图像数据采集及数据回读进行了硬件设计,并且对其时序控制逻辑进行了设计与优化。通过验证,此通道的设计保证了双路高速LVDS图像数据接收和数据回读的正确性,完成了数据记录和数据回收的功能。
In order to analyze the image parameters of the missile in the launching process, data need to be stored so that they can be read back. In this paper, FPGA is designed as the core logic controller, and the hardware of the dual channel high-speed LVDS image data acquisition and data read back on the missile, also the timing control logic are designed and optimized. Through verification, the design of this channel guarantees the correctness of the double channel high-speed LVDS image data reception and data read back, and achieves the functions of data recording and data recovery.
作者
任勇峰
康曦
单彦虎
REN Yongfeng;KANG Xi;SHAN Yanhu(Education Science and Technology on Electronic Test ＆ Measurement Laboratory, North University of China, Taiyuan 030051, China)
出处
《实验室研究与探索》
CAS
北大核心
2018年第3期96-100,共5页
Research and Exploration In Laboratory
关键词
现场可编程门阵列
低压差分信号
图像数据
数据接收
数据回读
field-programmble gate array
low-voltage differential signaling（LVDS）
image data
data reception
data read back
