摘要
针对6 500 V SiC器件的阻断电压要求,采用有限元仿真软件对场限环终端结构进行了设计优化。相比于通常的恒定环间距增量场限环终端设计,本项研究采用三段不同的环间距增量终端环结构。该结构场限环终端的优势在于SiC器件表面的峰值电场强度控制在1MV/cm以下,体内的峰值电场强度在2.4MV/cm以下,有效减小了实际工艺中环注入窗口的工艺偏差引起的环间距拉偏对峰值电场强度的影响。环间距拉偏结果显示,在-0.2^+0.2μm的偏差范围内,器件表面(SiO_2/SiC交界处)的峰值电场强度并没有升高,只是峰值的位置发生了改变。最后利用了所设计的场限环终端进行了实际流片。测试结果显示,当施加6 500V的反向电压,漏电流小于10μA。
Field limiting rings（FLR）termination was designed and optimized through finite element simulation tool for 6 500 V blocking capability.Compared with the field limiting rings with constant spacing increment ever reported,three different spacing increments from the inner side to the outer side of the FLR termination were used in this work.The proposed structure has much lower surface electric field（〈1 MV/cm）and peak body electric field（2.4 MV/cm）,which greatly relieves the effect of lithography window on the electric field.The simulation results show that when the deviation was in the range of-0.2μm to 0.2μm,the peak surface electric field does not increase and the location of peak electric field varied accordingly.Finally,JBS diode was fabricated with the obtained field limiting rings termination.The measured results indicate that the leakage current was lower than 10μA with a reversely biased voltage of 6 500 V.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2018年第1期1-5,共5页
Research & Progress of SSE
