摘要
VDMOSFET(Vertical Double-diffused Metal Oxide Semiconductor)功率器件不同于传统数模集成电路中器件,除了基本的静态和交流特性以外,UIS(非箝位感性负载开关)雪崩耐量(Eas)也是功率器件重要的衡量指标。非箝位感性负载开关过程所引起的VDMOS器件失效是VDMOS在应用过程中最主要的失效形式。故而,提高非箝位电感开关雪崩耐量的研究具有极为重要的意义。本文通过对工艺及器件结构的优化,使VDMOSFET的UIS雪崩耐量在不增加工艺层次的条件下增加接近70%。
Power devices such as VDMOSFET etc. are different from traditional digital analog integrated circuits. The main failure form of VDMOS is under Unclamped Inductive Switching（UIS） condition, so there is a dedicated parameter for power devices to evaluate the quality of the device. The maximum energy of avalanche in single pulse （Eas） or in repetitive pulse is the important parameter to measure the UIS characteristics of VDMOS. Therefore, it is of great significance to improve VDMOS device＇s Eas.
出处
《科学技术创新》
2017年第16期55-56,共2页
Scientific and Technological Innovation
