摘要
为了实现高速数据流的跨时钟域传输,根据万兆以太网10Gbase-KR协议设计了一款性能稳定的弹性缓冲器,并对设计进行逻辑综合和门级仿真,验证了设计的正确性.该弹性缓冲器采用常半满控制方式,深度为16,数据传输速率为10Gbps,读写时钟频率为156.25 MHz,通过检测读写地址差值变换情况来比较读写速度,并自动插入或删除IDLE字符,以此调节弹性缓冲器读写速度完成时钟频率补偿,实现了高速数据流的跨时钟域正确传输.
An elastic buffer is designed to satisfy the need of clock domain crossing of the high-speed data flow based on the 10Gbase-KR ethernet protocol. Then the logical synthesis and gate-level simulation is conducted to demonstrate the design is correct. The elastic buffer is controlled with the normal half-full method, of which the depth is 16, the data transfer rate is 10Gbps, and the read-write clock frequency is 156. 25MHz. By detecting the changes of the difference between the reading and writing address, it can make a contrast with the reading and writing speed and automatically insert or delete the IDLE characters. In the way, it can adjust the elastic buffer to realize clock frequency compensation and the clock domain crossing of the high-speed data flow correctly.
出处
《微电子学与计算机》
CSCD
北大核心
2018年第3期14-18,共5页
Microelectronics & Computer
基金
国家科技重大专项(2016ZX01012101)
