摘要
为了适应图像传感系统日益提高的性能需求,采用E2V公司的低噪声CMOS图像传感器设计一种的集成度高、灵活简便的成像电路。该成像电路由电源模块、驱动模块、数据处理模块、时序控制模块等组成。FPGA作为主控芯片产生所需的驱动时序和控制信号,上位机通过千兆以太网卡对成像系统进行采集和控制,最后对成像系统进行噪声和成像测试,试验结果表明,在室温的条件下,8 ms积分时间系统的平均噪声为0.64LSB,可以满足需求。
The imaging circuit With flexible , simply and high integration based on E2V＇ low-noise CMOS image sensor is designed to meet the increasing performance requirements on imaging system. This circuit of imaging system consists of power module, driver module, data processing module, timing control module and so on. FPGA is used as the main control chip to generate the required drive timing and control signals and the upper computer drive and control the imaging system through the gigabit Ethernet card. Finally, the noise and imaging tests are carried out, and the experimental result shows that the system average noise of the 8ms integration time is 0.64LSB at room temperatures and meets requirement.
出处
《电子设计工程》
2018年第4期188-193,共6页
Electronic Design Engineering
