摘要
本文设计了一款基于SMIC 0.18μm混合信号CMOS工艺的14-bit数字自校准模数转换器.主DAC(MDAC)分三段式结构,将电容阵列分成高6位、中4位和低4位的结构.校准算法是采用数字电路实现,利用一定时序获取每一位电容对应的误差电压并将其转化为相应的数字码值.在正常的ADC转换阶段,将上述数字码值补偿到相应的主DAC上,从而达到了校准的目的,提高了DAC的线性度.电路设计基于Cadence平台进行仿真验证,仿真结果表明,在1.8V电压下,能够有效校准电容阵列的失配,ADC校准后有效位数达到13.4998bit.
A 14-bit Successive Approximation analog to digital converter with Digital Self-calibration technology is designed and fabricated with SMIC 0.18μm Mix-signal technology CMOS process in this research.The main DAC is divided into three stages,the capacitor array is divided into the upper 6 bits,the middle 4 bits and the lower 4 bits.The calibration algorithm is implemented by digital circuit,the error voltage corresponding to each capacitor is obtained by using a certain time sequence,and then is transformed into the corresponding digital code value.In the normal ADC conversion phase,the above digital code value is compensated to the corresponding MDAC so that the purpose of calibration is achieved,therefore the linearity of DAC is improved.The circuit is designed based on the cadence platform for simulation and verification.The simulation results show that the mismatch of the capacitor array is effectively calibrated at voltage 1.8 V,and after the calibration,the ADC can effectively reach more than 13.4998 bits.
出处
《北方工业大学学报》
2017年第5期27-31,86,共6页
Journal of North China University of Technology
关键词
SAR
模数转换器
数字自校准算法
SAR
analog-to-digitalconverter
digitalself-calibrationalgorithm
