摘要
本文为船舶自动识别系统射频直接采样(RF)后的AIS信号处理提供了可行性方案。该方案将CH87B(AIS1)和CH88B(AIS2)两个信道的信号通过两次数字下变频(DDC)搬移到基带上,并采用多级抽取滤波设计方法,分离出两个信道的低速率AIS信号。通过在Artix7系列的XC7A100T上进行了FPGA实现和大量反复测试后,结果表明,该设计有效减少了硬件资源的消耗,同时也达到了设计指标的要求。
A feasible scheme for the AIS signal based on the radio frequency （RF） A/D sampling is provided in this paper. The signals from the channels of CH87B（AIS1） and CH88B（AIS2） are moved to base- band frequency through the digital down conversion（DDC）. The multi-stage decimation filter is used to depart the two lowspeed AIS signals from each other. As a result, after the FPGA realization of the scheme by XC7A100T based on the Artix7 and plenty of test, it is effective for slowing down the ratio of the signal and reaching the design indices.
出处
《电子设计工程》
2017年第20期64-67,71,共5页
Electronic Design Engineering
关键词
软件无线电
中频采样
AIS信号
数字下变频
FPGA
software defined radio
intermediate frequency
AIS signal
digitalfrequency down conversion
FPGA
