摘要
设计了一种高速高精度的时钟占空比稳定电路。采用全差分连续时间积分器将时钟占空比量化为电压信号,积分器对占空比偏差的累积效应可使电路达到很高的调整精度。采用跨导运算放大器将电压信号转换为电流信号,并加载到输入时钟缓冲器上,改变其输出时钟的直流电平,从而调整输出时钟的占空比,避免了调整输出时钟上升/下降沿带来的较大抖动。采用TSMC 0.18μm CMOS工艺进行设计,电源电压为2V。当输入差分时钟频率为1.6GHz时,可以将占空比范围为20%~80%的输入时钟信号的占空比均调节至(50±0.5)%,且输出时钟抖动小于159.398fs,适用于超高速的信号处理系统。
A high speed and high precision clock duty cycle stabilizer circuit was designed.A fully differential continuous-time integrator was used to quantify the clock duty cycle to a voltage signal,and the cumulative effect of the duty cycle deviation from integrator had ensured that the circuit could achieve high precision adjustment.A transconductance amplifier was used to convert the voltage signal to a current signal.This current signal was loaded to the input clock buffer,and the DC level of its output clock was changed for the purpose of adjusting the duty cycle of output clock.This could avoid the high jitter brought by the traditional adjustment mode when the rising and falling edges of output were adjusted.The circuit was designed in the TSMC 0.18μm standard CMOS process at a power supply voltage of 2 V.When the input clock＇s differential frequency was 1.6 GHz and the input clock duty cycle＇s range was 20%-80%,the duty cycle of output clock had been adjusted to（50±0.5）%,and the output clock jitter was less than 159.398 fs.It＇s applicable to ultra high speed signal processing systems.
作者
邓红辉
储松
赵鹏程
DENG Honghui CHU Song ZFIAO Pengcheng(Institute of Microelectronics Design, Hefei University of Technology, Hefei 230009, P. R. Chin)
出处
《微电子学》
CSCD
北大核心
2017年第5期652-657,共6页
Microelectronics
基金
安徽省科技攻关项目(JZ2014AKKG0430)
中央高校基本科研业务费专项资金资助项目(2014HGCH0010)
关键词
占空比
连续时间积分器
跨运算导放大器
Duty cycle
Continuous-time integrator
Transconductance operational amplifier
